DDR4 UDIMM Memory Module Specifications

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Basic Info

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Incoterm:	FOB,CIF,EXW
Transportation:	Ocean,Land,Air,Express

Product Description

8GB 2666MHz 288-Pin DDR4 UDIMM

Revision History

Revision No.	History	Draft Date	Remark
1.0	Initial Release	Apr. 2022

Ordering Information Table

Model	Density	Speed	Organization	Component Composition
NS08GU4E8	8GB	2666MHz	1Gx64bit	DDR4 1Gx8 *8

Description
Hengstar Unbuffered DDR4 SDRAM DIMMs (Unbuffered Double Data Rate Synchronous DRAM Dual In-Line Memory Modules) are low power, high-speed operation memory modules that use DDR4 SDRAM devices. NS08GU4E8 is a 1G x 64-bit one rank 8GB DDR4-2666 CL19 1.2V SDRAM Unbuffered DIMM product, based on eight 1G x 8-bit FBGA components. The SPD is programmed to JEDEC standard latency DDR4-2666 timing of 19-19-19 at 1.2V. Each 288-pin DIMM uses gold contact fingers. The SDRAM Unbuffered DIMM is intended for use as main memory when installed in systems such as PCs and workstations.

Features
Power Supply: VDD=1.2V (1.14V to 1.26V)
VDDQ = 1.2V (1.14V to 1.26V)
VPP - 2.5V (2.375V to 2.75V)
VDDSPD=2.25V to 3.6V
Nominal and dynamic on-die termination (ODT) for data, strobe, and mask signals
Low-power auto self refresh (LPASR)
Data bus inversion (DBI) for data bus
On-die VREFDQ generation and calibration
On-board I2C serial presence-detect (SPD) EEPROM
16 internal banks; 4 groups of 4 banks each
Fixed burst chop (BC) of 4 and burst length (BL) of 8 via the mode register set (MRS)
Selectable BC4 or BL8 on-the-fly (OTF)
Databus write cyclic redundancy check (CRC)
Temperature controlled refresh (TCR)
Command/Address (CA) parity
Per DRAM Addressability is supported
8 bit pre-fetch
Fly-by topology
Command/Address latency (CAL)
Terminated control command and address bus
PCB: Height 1.23” (31.25mm)
Gold edge contacts
RoHS Compliant and Halogen-Free

Key Timing Parameters

MT/s	tCK (ns)	CAS Latency (tCK)	tRCD (ns)	tRP (ns)	tRAS (ns)	tRC (ns)	CL-tRCD-tRP
DDR4-2666	0.75	19	14.25	14.25	32	46.25	19-19-19

Address Table

Configuration	Number of bank groups	Bank Group Address	Bank Address	Row Address	Column Address	Page size
8GB(1Rx8)	4	BG0-BG1	BA0-BA1	A0-A15	A0-A9	1 KB

Functional Block Diagram

8GB, 1Gx64 Module (1Rank of x8)

Note:

1.Unless otherwize noted, resistor values are 15Ω±5%.

2.ZQ resistors are 240Ω ±1%.For all other resistor values refer to the appropriate wiring diagram.

3.EVENT_n is wired on this design. A standalone SPD may be used as well. No wiring changes are required.

Absolute Maximum Ratings

Absolute Maximum DC Ratings

Symbol	Parameter	Rating	Units	NOTE
VDD	Voltage on VDD pin relative to VSS	-0.3 ~ 1.5	V	1,3
VDDQ	Voltage on VDDQ pin relative to VSS	-0.3 ~ 1.5	V	1,3
VPP	Voltage on VPP pin relative to VSS	-0.3 ~ 3.0	V	4
VIN, VOUT	Voltage on any pin except VREFCA relative to VSS	-0.3 ~ 1.5	V	1,3,5
TSTG	Storage Temperature	-55 to +100	°C	1,2

Note:

1.Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.

This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

2.Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard.

3.VDD and VDDQ must be within 300mV of each other at all times; and VREFCA must be not greater than 0.6 x VDDQ, When VDD and VDDQ are less than 500mV; VREFCA may be equal to or less than 300mV.

4.VPP must be equal or greater than VDD/VDDQ at all times.

5.Overshoot area above 1.5V is specified in DDR4 Device Operation.

DRAM Component Operating Temperature Range

Symbol	Parameter	Rating	Units	Notes
TOPER	Normal Operating Temperature Range	0 to 85	°C	1,2
TOPER	Extended Temperature Range	85 to 95	°C	1,3

Notes:

1.Operating Temperature TOPER is the case surface temperature on the center / top side of the DRAM. For measurement conditions, please refer to the JEDEC document JESD51-2.

2.The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported. During operation, the DRAM case temperature must be maintained between 0 - 85°C under all operating conditions.

3.Some applications require operation of the DRAM in the Extended Temperature Range between 85°C and 95°C case temperature. Full specifications are guaranteed in this range, but the following additional conditions apply:

a). Refresh commands must be doubled in frequency, therefore reducing the Refresh interval tREFI to 3.9 µs. It is also possible to specify a component with 1X refresh (tREFI to 7.8µs) in the Extended Temperature Range. Please refer to the DIMM SPD for option availability.

b). If Self-Refresh operation is required in the Extended Temperature Range, then it is mandatory to either use the Manual Self-Refresh mode with Extended Temperature Range capability (MR2 A6 = 0b and MR2 A7 = 1b) or enable the optional Auto Self-Refresh mode (MR2 A6 = 1b and MR2 A7 = 0b).

AC & DC Operating Conditions

Recommended DC Operating Conditions

Symbol	Parameter	Rating			Unit	NOTE
Symbol	Parameter	Min.	Typ.	Max.	Unit	NOTE
VDD	Supply Voltage	1.14	1.2	1.26	V	1,2,3
VDDQ	Supply Voltage for Output	1.14	1.2	1.26	V	1,2,3
VPP	Supply Voltage for DRAM Activating	2.375	2.5	2.75	V	3